(1) FIELD OF THE INVENTION
This invention relates to the fabrication of integrated circuit devices and more particularly to a method of relieving stresses both in the metal layer and in the silicon substrate after metal lines formation.
(2) DESCRIPTION OF THE PRIOR ART
In order to get the smallest layout area, the metal lines at the periphery of a very large scale integrated circuit (VLSI) chip are always straight. Before the formation of the metal lines, the stress in the silicon substrate is released to a large extent by the thermal treatments and the generation of linear and/or planar defects. For instance, local oxidation of silicon to form active area islands, source/drain activation, BPSG densification and reflow, barrier layer formation, etc. are high-temperature processes. Point defects, linear defects and planar defects, e.g. vacancies, dislocation, stacking faults, are generated after thermal cycles as well as after other inadequate processes such as polysilicon etch, spacer etch, contact etch, etc.
In forming the metal lines, the metal is typically sputter deposited at a high temperature of about 400.degree. C. in order to achieve a good step coverage. The insulating layer and passivation layer are usually deposited and process treated, such as spin-on-glass curing, at temperatures higher than 400.degree. C. When the chip is cooled to room temperature, a strong compressive stress in the substrate and a strong tensile stress in the metal layer are generated. This is caused by the difference in the thermal coefficients of expansion of the substrate and the metal. For example, the thermal coefficients of expansion for silicon, silicon dioxide, and aluminum are about 4, 0.5, and 24.times.10.sup.-6 parts per million per .degree.C., respectively. The stresses are usually larger than 5.times.10.sup.9 dyne/cm.sup.2. The compressive stress in the silicon substrate will cause problems such as dislocations and stacking faults, junction leakage and junction breakdown voltages degradation. The tensile stress in the metal lines will cause problems such as stress migration, void formation, and reliability concerns. The considerable stress is also present in the intermetal dielectric layers and all overlayers to result in cracks, voids, metal stress migration, passivation failure, etc. These stresses are local functions and cannot be investigated by the global stress measurements taken after the metal has been patterned. The rugged topography within the chips can release most of these stresses; however, the straight metal lines especially at the periphery of the chips do not allow for stress release.
Referring now to FIG. 1A, there is illustrated a post-front-end-processed silicon substrate 1 on which a metal line 2 has been sputtered. (All layers and diffusions, etc., may be included in 1, but are not illustrated for the sake of simplicity). At 400.degree. C., the system is under no stress. As the chip is cooled to room temperature, the tendency is for the metal layer, 2, to contract more than the substrate layer, 1, as shown in FIG. 1B. Since the chip is not free to bend as illustrated in FIG. 1B, defects will occur such as a break, 3, in the metal line shown in FIG. 1C or crunching, 4, in the substrate as shown in FIG. 1D.